NVIDIA makes Vera Rubin support generally available in CUDA 13.5 NVIDIA makes Vera Rubin support generally available in CUDA 13.5

A toolkit upgrade has a driver counterpart

The release notes distinguish support for existing CUDA applications from access to new platform features. CUDA 13.x applications can use minor-version compatibility with drivers from branch 580 onward. CUDA 13.5 features and new platforms require R620 or newer drivers that support them. The toolkit no longer bundles a driver on Windows or Linux, so installing development tools and updating a machine's driver are separate operations. That distinction matters for a fleet with a shared operating-system image: changing the compiler package alone does not establish that a server supports the new hardware path.

Sharing builds on an earlier memory boundary

NVIDIA's October 27 description of CUDA 13.4 already covered memory-enforced sharing through its GPU Fractioning Operator and KAI Scheduler. Administrators could assign fixed memory or a guaranteed minimum with additional burst capacity. Its two execution modes made different trade-offs: time-slicing separated workload error domains, while streaming-multiprocessor sharing used one error domain. CUDA 13.5 adds weighted time-slicing and borrowing between multiprocessor partitions in MPS v3. These controls address how several jobs occupy a device after memory has been divided. For shared inference services, a memory allowance and a scheduling policy describe different parts of the same resource allocation. A single GPU uses one execution mode at a time, although different GPUs on a node can use different modes.

Library updates reach application code

The toolkit includes CCCL 3.5, whose standalone release appeared on October 7. It introduces public tuning interfaces for CUB algorithms, including choices about block size and vectorization for different GPU architectures. The release also adds reproducible floating-point scans for a fixed device, input and build configuration. Batched TopK can handle segments of different sizes and a separate selection count for each segment. Device-side reduction counts remove a host round trip when the amount of work is already known on the GPU. These are application-level changes: they affect how a developer expresses selection, aggregation and numerical work inside a larger pipeline.

Compilation moves earlier in the delivery process

CUDA 13.5 also extends nvprune with a precompile option that can turn intermediate GPU code into native machine code during packaging. That gives software distributors another place to perform compilation before an application starts. CUDA Tile gains multi-GPU communication through NVLink, and calls from Tile code into SIMT functions enter public preview. Together, these additions touch both the code a developer writes and the artifact shipped to a server.